1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to circuit elements, such as field effect transistors, and manufacturing techniques in which sophisticated surface topographies lead to deposition-related yield losses in the contact level of semiconductor devices.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements located on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies for advanced semiconductor devices are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips, graphic devices and the like, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially determines the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, may be a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
On the other hand, the continuous shrinkage of the gate length of planar transistor configurations may typically result in very sophisticated topographical configurations since the gate height may not be proportionally reduced in relation to the gate length unless very complicated process strategies are used for maintaining the desired overall gate conductivity and the ion blocking effect during the formation of drain and source regions of the transistors in which the gate electrode, in combination with a spacer structure, typically acts as an implantation mask. Consequently, upon further reducing the gate length in order to improve performance of the individual transistors and also increase overall packing density of the semiconductor devices, the space between neighboring gate electrode structures may also be reduced, thereby requiring sophisticated deposition techniques in an advanced manufacturing stage in order to reliably fill the space between the densely packed gate electrode lines. In advanced approaches, the reliable filling in of dielectric material between closely spaced gate electrode lines may, however, strongly depend on the overall manufacturing strategy, in particular when additional performance enhancing mechanisms are implemented in one or both type of transistors. For example, for a given gate length of field effect transistors, the performance thereof may be further increased by inducing a certain type of strain in the channel region of the transistors, which may have a strong effect on the resulting charge carrier mobility. For a standard crystallographic configuration, a compressive strain component in the channel region of P-channel transistors may significantly enhance the overall drive current capability due to an increase of the mobility of holes, which represent the dominant charge carrier in P-channel transistors. Similarly, a tensile strain component in N-channel transistors may result in a significant increase of electron mobility, thereby also improving the drive current capability. One efficient mechanism for increasing the strain locally in P-channel transistors is the incorporation of a strain-inducing semiconductor alloy, such as a silicon/germanium alloy, which may result in a significant compressive strain component. For this purpose, cavities may be selectively formed in the active regions of the P-channel transistors after the patterning of the basic gate electrode structures, and the cavities may be refilled with a crystalline silicon/germanium alloy, which may be grown on the remaining silicon base material, thereby obtaining the desired compressive strained state. Although these techniques provide a significant performance gain of P-channel transistors, it turns out that the incorporation of a strain-inducing semiconductor alloy in a very early manufacturing stage of the transistor element may further contribute to a very pronounced surface topography in depositing an interlayer dielectric material, in particular in isolation structures delineating the active regions of P-channel transistors, as will be explained in more detail with reference to FIGS. 1a-1m. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100, which comprises a substrate 101 in combination with a semiconductor layer 102, which may typically represent a silicon-based semiconductor material. The substrate 101 and the semiconductor layer 102 may represent a bulk configuration, i.e., the layer 102 may represent a portion of a crystalline semiconductor material of the substrate 101, while, in other cases, a buried insulating layer (not shown) may be formed between the semiconductor layer 102 and the substrate 101, thereby forming a silicon-on-insulator (SOI) configuration. Furthermore, dielectric layers 103 and 104 are provided above the semiconductor layer 102, wherein the layer 103 may typically be provided in the form of a silicon dioxide layer, while the layer 104 may be a silicon nitride layer. It is well known that silicon nitride may be efficiently removed selectively to silicon dioxide material on the basis of a plurality of etch recipes, while silicon dioxide may be removed selectively with respect to silicon material by etch chemistries such as hydrofluoric acid (HF) and the like. Thus, the layers 103 and 104 may be efficiently used for patterning the semiconductor layer 102 in order to form trench isolations therein. For this purpose, an etch mask 105, such as a resist mask and the like, is formed above the layer 104 and comprises an appropriate opening 105A in order to define the lateral position and size of a trench to be formed in the semiconductor layer 102.
The device 100 as illustrated in FIG. 1a may be formed on the basis of well-established process strategies, i.e., the layer 103 may be deposited or may be formed by oxidation, followed by the deposition of the silicon nitride material 104, which may be accomplished by using thermally activated chemical vapor deposition (CVD) recipes, plasma enhanced CVD and the like. Thereafter, the etch mask 105 may be provided, for instance, on the basis of advanced lithography techniques. Thereafter, well-established etch techniques may be applied in order to etch through the layers 104 and 105 and thereafter selecting an appropriate anisotropic etch chemistry for etching into the semiconductor layer 102 on the basis of the etch mask 105 and/or the patterned layers 103 and 104.
FIG. 1b schematically illustrates the device 100 with a trench 102T formed in the semiconductor layer 102 and in the layers 103 and 104. It should be appreciated that the trench 102T may thus laterally delineate corresponding semiconductor regions of the layer 102, wherein, for instance, a first active region 102A may be laterally separated from a second active region 102B. In this respect, an active region is to be understood as a portion of the semiconductor layer 102 in which PN junctions of one or more transistor elements are to be formed in a later manufacturing stage. It should be appreciated that the isolation trench 102T may extend down to a buried insulating layer if an SOI configuration is considered.
FIG. 1c schematically illustrates the device 100 in a manufacturing stage in which a fill material 105, such as a silicon dioxide material, is provided so as to reliably fill the trench 102T, which may be accomplished on the basis of well-established CVD techniques. It should be appreciated that, if required, additional process steps, such as an oxidation step and the like, may be performed in order to obtain a certain degree of corner rounding and the like, if required.
FIG. 1d schematically illustrates the device 100 after the removal of any excess material of the layer 105 (FIG. 1c) which may be accomplished on the basis of chemical mechanical polishing (CMP), thereby forming a trench isolation structure 120. During the removal process, the silicon nitride layer 104 may act as an efficient stop material. Thereafter, depending on the degree of over-polish applied during the preceding removal process, the layer 104 may be removed by a further CMP process and/or an etch process, wherein undue exposure of the active regions 102A, 102B may be prevented on the basis of the silicon dioxide layer 103. Next, the layer 103 may be removed, for instance, by any appropriate wet chemical etch recipe, thereby also removing a portion of the trench isolation structure 120.
FIG. 1e schematically illustrates the semiconductor device 100 after the above-described process sequence, wherein the trench isolation structure 120 may have substantially the same height as the active regions 102A, 102B, which may be accomplished by controlling the etch process for removing layer 103 (FIG. 1d) when a pronounced difference in height level may have been created upon removing the layer 104 (FIG. 1d).
FIG. 1f schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a plurality of gate electrode structures 150A, 150B and 150C are formed above the active regions 102A, 102B and above the isolation structure 120. It should be appreciated that the gate electrode structures 150C formed above the isolation structure 120 may be considered as “gate electrode structures” since these structures may typically extend in a direction perpendicular to the drawing plane of FIG. 1f into a further active region and may act as a gate electrode. Similarly, depending on the overall device configuration, the gate electrode structures 150A, 150B formed above the active regions 102A, 102B, respectively, extend above an isolation structure and may extend to a further active region, if required. The gate electrode structures 150A, 150B, 150C may comprise an electrode material 151, such as a silicon material, a silicon/germanium material and the like, possibly in combination with other materials, such as metal-containing materials and the like. Furthermore, a gate insulation layer 152 may be provided, at least in the gate electrode structures 150A, 150B, which separates the electrode material 151 from the underlying active regions 102A, 102B. Depending on the process for forming the gate insulation layer 152, the electrode material 151 may be substantially directly formed on the trench isolation structure 120. In the example shown, it may be assumed that at least a portion of the gate insulation layer 152 may be formed by deposition and may thus also be provided on the trench isolation structure 120 and thus in the gate electrode structures 150C. Furthermore, a dielectric cap material 153, such as a silicon nitride material, may be formed on the electrode material 151. Moreover, as previously explained, the active regions 102A, 102B may represent, in combination with the intermediate trench isolation structure 120, an area for providing P-channel transistors as densely packed circuit elements so that the spacing between neighboring gate electrode structures may be selected in accordance with the overall design rules and may be in the range of approximately 100 nm and less for a gate length of approximately 50 nm and less. It should be appreciated that the gate length of the gate electrode structures 150A, 150B, 150C may be considered as the horizontal extension of the electrode material 151. Consequently, for a given height of the gate electrode structures 150A, 150B, 150C of approximately 80-120 nm, a pronounced aspect ratio, i.e., a ratio of height or depth to width, may be defined which may even be increased during the further processing, as will be explained later on. Moreover, during the further processing, a performance increasing mechanism in the form of an embedded silicon/germanium alloy is to be incorporated into the active regions 102A, 102B, wherein the corresponding process sequence has been identified as a major source for further increasing the aspect ratio for the gate electrode structures 150C formed above the trench isolation structure 120.
In order to incorporate an appropriate strain-inducing semiconductor alloy, such as a silicon/germanium alloy, for P-channel transistors, the gate electrode structures 150A, 150B, 150C in a corresponding P region have to be appropriately protected, while at the same time exposing a significant portion of the active regions 102A, 102B. For this purpose, corresponding offset spacer elements 154, for instance comprised of silicon nitride, are typically formed on sidewalls of the gate electrode structures 150A, 150B, 150C. On the other hand, other device areas, i.e., areas in which N-channel transistors and corresponding isolation structures are provided, may be reliably covered by a silicon nitride layer.
The semiconductor device 100 as illustrated in FIG. 1f may be formed on the basis of the following processes. After completing the trench isolation structure 120 or in any appropriate manufacturing stage prior to forming the structure 120, an appropriate basic dopant concentration may be introduced into the active regions 102A, 102B, such as an N-type doping species, in order to establish the basic transistor characteristics. Next, material for the gate insulation layers 152 and for the electrode material 151 may be formed, for instance, by oxidation, deposition and the like, using well-established process techniques. It should be appreciated that, in sophisticated applications, a high-k dielectric material may be incorporated in the gate insulation layers 152, if required. Thereafter, sophisticated lithography and etch techniques are applied in order to pattern the electrode material 151 and the gate insulation layers 152 in accordance with the design rules. It should be appreciated that the cap material 153 may also be patterned during the corresponding process sequence. Next, a silicon nitride material may be deposited with an appropriate thickness and may be subsequently patterned, thereby forming the offset spacer elements 154, while other device areas may be masked, such as active regions of N-channel transistors and corresponding isolation structures.
FIG. 1g schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As shown, cavities 106 are formed in the active regions 102A, 102B, which may be accomplished by performing any appropriate etch process with a high degree of selectivity with respect to silicon dioxide and silicon nitride material. For example, a plurality of plasma-assisted etch recipes are well established in the art for etching silicon material selectively with respect to silicon nitride and silicon dioxide. It should be appreciated that forming the cavities 106 and forming the offset spacer elements 154 may be accomplished in a single etch sequence by appropriately adjusting the etch chemistry upon exposing the active regions 102A, 102B during the etch process for forming the spacer elements 154. It should be appreciated that the size and shape of the cavities 106 may be determined by the width of the offset spacer 154 and by corresponding characteristics of the etch process, since a certain degree of under-etching may be applied, if considered appropriate, which may be accomplished by changing the etch chemistry at any appropriate phase of the etch process and the like.
As is well known, after performing etch processes based on an etch mask and a complex etch chemistry, typically, significant contamination of the device surface may have occurred which may significantly influence the further processing, in particular when critical process steps such as a selective epitaxial growth process has to be performed as a next step. For this reason, efficient cleaning processes may have to be applied, in particular after the cavity etch process, in order to prepare the exposed surface portions for the subsequent selective epitaxial growth process. For instance, very efficient cleaning recipes may be based on hydrofluoric acid, which, however, may also efficiently remove silicon oxide-based materials and may thus contribute to a pronounced material erosion in the isolation structure 120.
FIG. 1h schematically illustrates the semiconductor device 100 when exposed to a reactive process ambient 107, for instance based on HF, in order to clean exposed surface portions. As explained above, a significant material erosion may occur in the isolation structure 120, thereby forming a recess 120A, the final size of which may significantly depend on the parameters and the duration of the cleaning treatment 107. Since a less efficient and thus less aggressive cleaning effect may have a pronounced influence on the subsequently performed selective epitaxial growth process, a compromise has to be found between material erosion, as indicated by the dashed lines, and a desired degree of removal of contaminations for the subsequent epitaxial growth process.
FIG. 1i schematically illustrates the device 100 with a strain-inducing semiconductor alloy, such as a silicon/germanium alloy 108, formed in the active regions 102A, 102B. The semiconductor alloy 108 may be formed by selective epitaxial growth techniques in which process parameters are selected such that material deposition may be substantially restricted to exposed crystalline semiconductor areas, while a material deposition on dielectric surface areas, such as the encapsulated gate electrode structures 150A, 150B, 150C and the trench isolation structure 120 is substantially suppressed.
FIG. 1j schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which the offset spacers 154 and the cap material 153 (FIG. 10 are removed, which may be accomplished by well-established selective wet chemical etch recipes, such as hot phosphoric acid and the like. During the removal of these components, a corresponding silicon nitride mask layer may also be removed from other device areas, such as N-channel transistor areas and the like, as previously explained. Based on the configuration as shown in FIG. 1j, the further processing may be continued by completing the basic transistor configuration, for instance, by forming drain and source regions on the basis of an appropriate sidewall spacer structure.
FIG. 1k schematically illustrates the semiconductor device 100 in an advanced manufacturing stage in which transistors 160A, 160B are provided in and above the active regions 102A, 102B. The transistors 160A, 160B comprise drain and source regions 161, the vertical and lateral dopant profile of which may be defined on the basis of a sidewall spacer structure 155. For example, the width 155A of the spacer structures 155 of the transistors 160A, 160B may be used for defining deep drain and source areas in the drain and source regions 161. On the other hand, a width 155C of the spacer structure 155 formed on sidewalls of the gate electrode structures 150C may be increased due to the presence of the recess 120A formed in the trench isolation structure 120 during the previous processing, as discussed above. Consequently, the resulting aspect ratio between the gate electrode structures 150C above the isolation structure 120 may be further increased due to the recess 120A and due to the fact that the effective spacer width 155C may be greater than the effective width between the gate electrode structures 150A and 150C or the gate electrode structures 150B and 150C.
The semiconductor device 100 as illustrated in FIG. 1k may be formed on the basis of the following processes. First, a portion of the spacer structure 155 (not shown), for instance in the form of a moderately thin spacer element, may be provided and corresponding implantation processes may be performed, for instance for forming extension regions, counter-doped regions or halo regions and the like, as may be required for obtaining the complex dopant profile at a channel region 162 of the transistors 160A, 160B. Next, more spacer elements of the spacer structure 155 (not shown) may be formed, depending on the overall complexity of the drain and source regions 161, with corresponding intermediate implantation processes. The spacer elements may be formed by depositing a silicon nitride material, possibly in combination with an etch stop liner, and performing well-established anisotropic etch processes. Consequently, upon depositing the spacer material and etching the same, the different spacer widths 155A, 155C may be generated. After a final anneal process for activating the dopant species and re-crystallizing implantation-induced damage, the further processing may be continued, for instance, by performing a further cleaning process, preparing exposed surface portions for the deposition of a refractory metal, such as nickel and the like. Also in this case, a material loss may be generated in the recess 120A, however, at a lesser degree compared to the previously described cleaning process 107 (FIG. 1h).
FIG. 11 schematically illustrates the semiconductor device 100 with metal silicide regions 163 formed in the drain and source regions 161 of the transistors 160A, 160B. Moreover, metal silicide regions 156 may be formed in the gate electrode structures 150A, 150B, 150C. The metal silicide regions 163, 156 may be formed on the basis of well-established process techniques in which one or more refractory metals, such as nickel, platinum and the like, may be deposited and may be reacted with the semiconductor material in the drain and source regions 161. Furthermore, during the preceding cleaning process, the recess 120A may be further increased, as indicated by the dashed lines.
FIG. 1m schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a first dielectric material 130 is formed above and between the gate electrode structures 150A, 150B, 150C, which may be provided in the form of a silicon nitride material. Moreover, a further interlayer dielectric material, such as a silicon dioxide material 131, may be formed above the material 130 and may thus form an interface between the device level comprising the transistors 160A, 160B and the gate electrode structures 150C and a metallization system to be formed above the material 131. The layer 130 may also act as an etch stop material for patterning the dielectric material 131, when forming openings therein so as to connect to certain contact regions of the transistors 160A, 160B and also to other active regions, above which also the gate electrode structures 150C may extend, as previously explained. Consequently, the material 130 may have to meet specific requirements with respect to layer thickness and material composition, which may, however, not be compatible with the requirements imposed by the complicated surface topography caused by the recess 120A in the trench isolation structure 120. That is, for a desired layer thickness that is selected so as to obtain reliable filling between the gate electrode structures 150A, 150C, the significantly increased aspect ratio between the gate electrode structures 150C may result in the generation of deposition-related irregularities, such as a void 130A, which may thus extend in a direction perpendicular to the drawing plane of FIG. 1m, for instance, the void 130A may extend to active regions. Consequently, during the further processing of the device 100, i.e., forming contact openings in the dielectric materials 131 and 130, the void 130A may be opened and upon filling the contact openings with an appropriate material, such as tungsten, this material may also be deposited within the void 130A and may extend from an active region into the isolation structure 120 and possibly into a further active region, thereby causing a leakage path or even a short circuit between adjacent contact elements provided along a direction perpendicular to the drawing plane of FIG. 1m. Consequently, the presence of the void 130A may result in a significant yield loss during the complex patterning process for forming contact elements in the dielectric materials 131 and 130.
The situation may become even more complex when the dielectric material 130 may have to be provided in the form of a highly stressed dielectric material since, in this case, the process parameters may have to be selected on the basis of a significantly reduced range in order to obtain the desired internal stress level upon depositing the material in a desired highly stressed state, such as a highly compressively stressed state. Furthermore, in order to be an efficient strain-inducing mechanism, the thickness of the layer 130 may have to be selected as large as possible, thereby further increasing the probability of creating the void 130A. Consequently, the pronounced surface topography caused by the recess 120A may not be compatible with efficient strain-inducing mechanisms, such as a strained embedded semiconductor alloy and/or a strain-inducing dielectric material, such as the layer 130.
In some conventional approaches, the aspect ratio above the isolation structure 120 may be reduced by, for instance, removing at least a significant portion of the spacer structure 155 prior to the deposition of the material 130. It turns out, however, that a removal or a reduction in size of the spacer structure 155 may have a strong effect on the performance of P-channel transistors and N-channel transistors with a strong correlation to the actually applied device configuration and process strategy. For example, the DC (direct current) characteristics may be significantly affected by a spacer removal, for instance applying stress memorization techniques in N-channel transistors, by providing various strain-inducing mechanisms in P-channel transistors and the like, so that a high degree of transistor variability may be introduced in exchange for improving the deposition conditions during the deposition of the material 130. Consequently, a corresponding approach may be less than desirable.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.